30 lines
1.2 KiB
Diff
30 lines
1.2 KiB
Diff
From 1af27671f62ce919f1fb76082ed81f71cb090989 Mon Sep 17 00:00:00 2001
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From: Chris Morgan <macromorgan@hotmail.com>
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Date: Wed, 18 Oct 2023 10:33:55 -0500
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Subject: [PATCH] clk: rockchip: rk3568: Add PLL rate for 292.5MHz
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Add support for a PLL rate of 292.5MHz so that the Powkiddy RGB30 panel
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can run at a requested 60hz (59.96, close enough).
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I have confirmed this rate fits with all the constraints
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listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
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2 Clock & Reset Unit (CRU)."
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Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
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Link: https://lore.kernel.org/r/20231018153357.343142-2-macroalpha82@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3568.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/drivers/clk/rockchip/clk-rk3568.c
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+++ b/drivers/clk/rockchip/clk-rk3568.c
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@@ -72,6 +72,7 @@ static struct rockchip_pll_rate_table rk
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RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
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RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
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RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),
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+ RK3036_PLL_RATE(292500000, 1, 195, 4, 4, 1, 0),
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RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),
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RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
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RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
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