32 lines
1.3 KiB
Diff
32 lines
1.3 KiB
Diff
From dafebd0f9a4f56b10d7fbda0bff1f540d16a2ea4 Mon Sep 17 00:00:00 2001
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From: Alibek Omarov <a1ba.omarov@gmail.com>
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Date: Wed, 14 Jun 2023 16:47:50 +0300
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Subject: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
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PLL rate on RK356x is calculated through the simple formula:
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((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)
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The PLL rate setting for 78.75MHz seems to be copied from 96MHz
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so this patch fixes it and configures it properly.
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Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
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Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")
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Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
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Link: https://lore.kernel.org/r/20230614134750.1056293-1-a1ba.omarov@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3568.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/clk/rockchip/clk-rk3568.c
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+++ b/drivers/clk/rockchip/clk-rk3568.c
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@@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk
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RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
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RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
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RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
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- RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
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+ RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
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RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
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{ /* sentinel */ },
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};
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