// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

/dts-v1/;
#include "mt7981b-cmcc-rax3000m.dts"

/ {
	model = "CMCC RAX3000M NAND version (custom U-Boot layout)";
	compatible = "cmcc,rax3000m-nand-ubootmod", "mediatek,mt7981";

	aliases {
		label-mac-device = &gmac1;
	};
};

&gmac0 {
	nvmem-cells = <&macaddr_factory_2a 0>;
	nvmem-cell-names = "mac-address";
};

&gmac1 {
	nvmem-cells = <&macaddr_factory_24 0>;
	nvmem-cell-names = "mac-address";
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_flash_pins>;
	status = "okay";

	spi_nand: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-nand";
		reg = <0>;

		spi-max-frequency = <52000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		mediatek,nmbm;
		mediatek,bmt-max-ratio = <1>;
		mediatek,bmt-max-reserved-blocks = <64>;

		partitions: partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "BL2";
				reg = <0x00000 0x100000>;
				read-only;
			};

			partition@100000 {
				label = "u-boot-env";
				reg = <0x100000 0x80000>;
			};

			factory: partition@180000 {
				label = "Factory";
				reg = <0x180000 0x200000>;

				compatible = "nvmem-cells";
				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					macaddr_factory_24: macaddr@24 {
						compatible = "mac-base";
						reg = <0x24 0x6>;
						#nvmem-cell-cells = <1>;
					};

					macaddr_factory_2a: macaddr@2a {
						compatible = "mac-base";
						reg = <0x2a 0x6>;
						#nvmem-cell-cells = <1>;
					};
				};
			};

			partition@380000 {
				label = "FIP";
				reg = <0x380000 0x200000>;
			};

			partition@580000 {
				label = "ubi";
				reg = <0x580000 0x7200000>;
			};
		};
	};
};

&pio {
	spi0_flash_pins: spi0-pins {
		mux {
			function = "spi";
			groups = "spi0", "spi0_wp_hold";
		};

		conf-pu {
			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
		};

		conf-pd {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
		};
	};
};

&wifi {
	mediatek,mtd-eeprom = <&factory 0x0>;
};