53 lines
2.2 KiB
Diff
53 lines
2.2 KiB
Diff
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From 6e69052f01d9131388cfcfaee929120118a267f4 Mon Sep 17 00:00:00 2001
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From: Sascha Hauer <s.hauer@pengutronix.de>
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Date: Wed, 26 Jan 2022 15:55:47 +0100
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Subject: [PATCH] clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference
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clock on rk3568
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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On the rk3568 we have this (simplified) situation:
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.--------. .-----. .---------.
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-| hpll |--.--| /n |----|dclk_vop0|-
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`--------´ | `-----´ `---------´
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| .-----. .---------.
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`--| /m |----|dclk_vop1|-
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| `-----´ `---------´
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| .---------.
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`-------------|hdmi_ref |-
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`---------´
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For the HDMI to work the HDMI reference clock needs to be the same as the
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pixel clock which means the dividers have be set to one. The last patch removed
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the CLK_SET_RATE_PARENT flag from the pixel clocks which means the hpll is not
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changed on pixel clock changes. In order to allow the HDMI controller to
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set a suitable PLL rate we now add the CLK_SET_RATE_PARENT flag to the
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HDMI reference clock. With this the flow becomes:
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1) HDMI controller driver sets the rate to its pixel clock which means
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hpll is set to the pixel clock
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2) VOP2 driver sets dclk_vop[012] to the pixel clock. As this can't change
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the hpll clock anymore this means only the divider is adjusted to the
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desired value of dividing by one.
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Link: https://lore.kernel.org/r/20220126145549.617165-26-s.hauer@pengutronix.de
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3568.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/clk/rockchip/clk-rk3568.c
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+++ b/drivers/clk/rockchip/clk-rk3568.c
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@@ -1568,7 +1568,7 @@ static struct rockchip_clk_branch rk3568
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RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
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GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,
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RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
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- MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0,
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+ MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT,
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RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
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};
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